Development And Optimization Of Electric-Double-Layer Gated Transistors Based On Low-Dimensional Materials: Gate-All-Around Inas Nanowire Arrays And Graphene Channels
- - =#n/a
- - Applied And Theoretical Physics
- - Biosciences
- - Chemistry And Materials Science
- - Computer Science, It & Applications
- - Earth System Sciences: Geography & Geology
- - Economics And Business Studies
- - Educational Research, Teaching And Learning
- - Environmental Engineering And Science
- - Ethics And Philosophy
- - Historical And Archaeological Studies
- - Journalism, Media And Digital Communication
- - Language Studies And Linguistic Sciences
- - Legal Studies
- - Mathematics, Probability And Statistics
- - Mechanical And Manufacturing Engineering
- - Medical And Biomedical Research
- - Nutrition And Food: Science And Technology
- - Pharmacology And Pharmaceutical Studies
- - Plant And Agricultural Sciences
- - Political Science And Public Policy
- - Power And Electrical Systems Engineering
- - Psychology And Mental Health
- - Social Sciences And Sociology
- - Structural, Geotechnical And Civil Engineering
Book Details :
Development And Optimization Of Electric-Double-Layer Gated Transistors Based On Low-Dimensional Materials: Gate-All-Around Inas Nanowire Arrays And Graphene Channels